High bandwidth chip-to-chip interconnection is a crucial part of many systems today. High speed inputs/outputs (I/Os) are extensively used in server processors, memory-central processing unit (CPU) interfaces, multiprocessor systems, and gaming applications. With increasing speed of on-chip data processing, there is an increasing demand for higher data rates. These high speed I/Os must also be capable of supporting low cost package and board technologies which introduce large signal degradation through bandwidth loss, reflection, and crosstalk.
Equalization of high-speed serial links has evolved to compensate inter-symbol interference (ISI) caused by frequency-dependent attenuation found in interconnects. Pre-emphasis-based equalization in the transmitter and decision feedback equalization in the receiver figure prominently in overcoming signal degradation and improving Bit Error Rate (BER). Currently, one challenge of equalization is minimizing power consumption while still improving signal integrity in the presence of attenuation and reflections.
Transmitters are a significant portion of the serial link power budget. The transmitter is required to drive enough power over lossy interconnects to meet minimum receiver sensitivity requirements. The use of amplitude pre-emphasis techniques, such as feed forward equalization, increases the power consumption and chip area and places additional demands on the dynamic range of the transmitter. Also, in a transmission system with high cross-talk between the channels, especially the near end cross talk where a transmitter is leaking into a neighboring receiver, amplitude pre-emphasis will enhance the high frequency cross-talk of the victim receiver which implies that its signal to noise ratio will be degraded.
In view of the foregoing, a growing need has been recognized in connection with improving upon the shortcomings and disadvantages presented by conventional arrangements.